Commit graph

23808 commits

Author SHA1 Message Date
Niccolò Maggioni
be71e3d019 arch/arm/rp2040: Fix typos in ADC and GPIO macros usage
The strings "RPC2040" and "RP2040_IO_BANK0_GPIO0", presumably typos,
were used in place of respectively "RP2040" and "RP2040_IO_BANK0_GPIO".

Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
2025-08-13 13:18:32 +02:00
Côme VINCENT
a4b17a2d14 arch/stm32h7: Fix timer capture
This patch fixes an incorrect call to stm32_cap_initialize() in
stm32_bringup.c: the call was made without the channel parameter.
Instead of adding the channel in the call, the channel is selected by
stm32_cap_gpio() (first available channel).

This patch also fixes incorrect driver registration in
drivers/timers/capture.c: the driver was registered with the wrong
name (/dev/cap -> /dev/capture). Also added more error checking in
cap_register_multiple().

Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
2025-08-12 20:21:14 +08:00
lipengfei28
5bba78ef85 arch/arm64: imx9 add pci dma space and pci outbound space
pci dma space used for pci inbound addr
pci outbound and outbound space need create page table

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2025-08-11 23:24:04 +08:00
Serg Podtynnyi
2e7f75f6e0 arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)
Chip name   : rp23xx-rv
Board name  : raspberrypi-pico-2-rv
Arch        : risc-v

Changes from ARM rp23xx impl

- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
2025-08-11 08:56:27 +08:00
Alan Carvalho de Assis
d218334baa boards/arcx-socket-grid: Add support to USBHOST and USBDISK
This PR add support to USBHOST on iMXRT1052 ARCX-Socket-Grid board
and add a USBDISK board config example.

Signed-off-by: Alan C. Assis <acassis@gmail.com>
2025-08-09 17:12:48 -03:00
Alan Carvalho de Assis
33e25738e5 arch/imxrt: Removed not defined imxrtimxrt_virtramaddr_async_setup
This function prototype was defined as static but the function
never was created or used.

Signed-off-by: Alan C. Assis <acassis@gmail.com>
2025-08-09 17:12:48 -03:00
Alan Carvalho de Assis
732a31c2bf arch/arm/imxrt: Fix incorrect symbol on imxtrt_ehci
Signed-off-by: Alan C. Assis <acassis@gmail.com>
2025-08-09 17:12:48 -03:00
Alan Carvalho de Assis
e26936b262 arch/arm/imxrt: Fix missing symbols on Kconfig
Signed-off-by: Alan C. Assis <acassis@gmail.com>
2025-08-09 17:12:48 -03:00
kywwilson11
821b067a60 arch/arm/stm32h5: Fix STM32H5 FDCAN Driver and Add Test Files
Primary Changes
1. Add Kconfig options to select FDCAN1 and FDCAN2.
2. Fix Make.defs to use CONFIG_STM32H5_FDCAN_CHARDRIVER
3. Add FDCAN clock seleection code to stm32h5xx_rcc.c
4. Add fdcan1 config for nucleo-h563zi board.
5. Add FDCAN clock configuration and GPIOs to nucleo-h563zi board.h.
6. Added supporting code (stm32_can.c, stm32_bringup.c changes)
   for fdcan1 config.

Changed can device to start at 0. FDCAN1  = /dev/can0, FDCAN2 = /dev/can1. Enable FDCAN mode for nucleo-h563zi:fdcan1 config.

Removed ampersand from comment block
2025-08-08 19:50:28 +02:00
Côme VINCENT
2771df6250 arch/arm/stm32h7: Port timer capture driver from stm32
This commit introduces a timer capture driver for the STM32H7 series
ported from the STM32 F series.

The main changes include:
- A new generic timer capture driver for STM32H7.
- A lower-half driver to integrate with the NuttX capture subsystem.
- Kconfig options to enable and configure capture for various timers.
- Pin definitions for TIM1-4 capture inputs on the nucleo-h743zi.
- An update to `cap_register_multiple` to handle multiple device registration.
- An update to `stm32_bringup` to register the capture drivers.

The current implementation is based on a driver originally for PWM input,
and as such, it calculates duty cycle and frequency. It is also limited
to a single capture channel per timer.

The original implementation's `stm32_cap_init` in
`arch/arm/src/stm32h7/stm32_capture.c` has been modified to accept a
channel number instead of using a hardcoded 0 through
`STM32_CAP_CHANNEL_COUNTER`.

This serves as a foundation for future development of more comprehensive
input capture capabilities on STM32H7 platforms.

Tested by polling and reading `/dev/cap0-4` with
`ioctl(fds[i], CAPIOC_FREQUENCE, freq)` while sending a square wave signal to
appropriate pins and checking frequency.

Also tested by bypassing upper half driver and setting up capture on
TIM4 channels 1-4 as explained in #16762.

Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
2025-08-07 10:46:39 -03:00
Eren Terzioglu
1c0e1698cd bugix/risc-v/esp32c6: Fix build error of LP_I2C
Fix build error of LP_I2C for esp32c6

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-08-05 08:00:12 -03:00
Konstantin Tyurin
85923c1797 arch/arm/stm32f0l0g0/: Fix I2C IRQ numbers
This patch sets a correct interrupt vector number
for each I2C controller.

Signed-off-by: Konstantin Tyurin <konstantin@pluraf.com>
2025-08-05 12:18:14 +02:00
Jukka Laitinen
9cda3ce216 arch/*/*_sigdeliver.c: Fix a race condition is signal delivery for SMP
This fixes the same issue for other targets, which was already fixed for
xtensa in commit 50d94863.

After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[xx]) will enable them if they were
enabled in the context.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-04 21:11:13 +08:00
kywwilson11
163bf0a906 arch/arm/stm32h5: Use double-buffer for ADC DMA in Circular Mode
Clear dma interrupt flags as before.

Change HTEF to HTF, fixes typo.

Remove ALL_FLAGS define. Clear CXFCR with all 1s like other instances do.

Handle half-transfer interrupt only if in circular mode.

Add ADC_HAVE_DMA guard around adc_rstart_dma. It is needed because priv->circular is guarded by ADC_HAVE_DMA.
2025-08-01 22:57:31 +08:00
Jukka Laitinen
50d94863f2 arch/xtensa: Fix a race condition in xtensa_sig_deliver for SMP
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[REG_PS]) will enable them if they were
enabled in the context.

Any interrupt on this cpu before xtensa_context_restore() would set
the rtcb->xcp.regs to NULL, causing a crash in context restore.

Fix this by calling leave_critical_section(up_irq_save()) instead.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
2025-08-01 08:54:39 -03:00
Alan Carvalho de Assis
59dc9a3884 arch/arm/imxrt: Initial modification to support two USB Controllers
Many iMXRT MCUs have internally two USB OTG controllers, however
NuttX currently only supports one USB controllers. This patch will
prepare the "house" to support both ports at same time.

Signed-off-by: Alan C. Assis <acassis@gmail.com>
2025-07-31 08:04:31 +02:00
Michal Lenc
cbfaf4224a arch/arch/src/samv7: add support for PIC32CZ CA70 series
PIC32CZ CA70 family is pin to pin and binary compatible with
SAMV70/SAME70 families, therefore the support is placed in samv7
directory. The only difference is larger RAM memory compared to SAM
families.

Signed-off-by: Michal Lenc <michallenc@seznam.cz>
2025-07-30 19:28:07 +08:00
Shanmin Zhang
5a91b1b0ee x86_64: allow specifying alternative compilers via CROSSDEV, rather than restricting to specific compiler
Test:

git clone -b dev -depth 1 https://github.com/open-vela/prebuilts_gcc_windows-x86_64_x86_64-none-elf.git ${HOME}/x86_64-none-elf
export CROSSDEV=${HOME}/x86_64-none-elf/bin/x86_64-none-elf-
./tools/configure.sh -l qemu-intel64:nsh
make

Output:

Create version.h
LN: platform/board to /home/shanmin/git/nuttx-apps/platform/dummy
Register: hello
Register: dd
Register: nsh
Register: sh
Register: ostest
LD: nuttx

Signed-off-by: Shanmin Zhang <zhangshanmin@xiaomi.com>
2025-07-30 02:41:29 +08:00
Shanmin Zhang
57d5d87d46 x86_64: Add the -Wa,--divide option for all x86_64 assemblers
Signed-off-by: Shanmin Zhang <zhangshanmin@xiaomi.com>
2025-07-30 02:41:29 +08:00
simbit18
a0c5d035d7 arm: CMake build for the i.MX RT series implemented.
CMake added board ARCX Socket Grid

Signed-off-by: simbit18 <simbit18@gmail.com>
2025-07-30 02:41:08 +08:00
lipengfei28
44016fbe77 arch/arm64/imx9: add imx95 support
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
2025-07-28 09:58:02 -03:00
kywwilson11
4995c836f3 arch/arm/stm32h5: Add DMA Support to STM32H5 Serial Driver
Style fixes.
2025-07-26 20:57:26 +08:00
YAMAMOTO Takashi
69bcbfb207 esp32s3_extraheaps.c: add a missing include for xtensa_imm_initialize
Signed-off-by: YAMAMOTO Takashi <yamamoto@midokura.com>
2025-07-25 15:51:38 +08:00
kywwilson11
cbd033ae90 arch/arm/stm32h5: Initial Driver for STM32H5 Digital Temperature Sensor (DTS)
- Committing initial code for DTS. Missing ISR. Works for PCLK1. Cannot get to work for LSE.
- Pushing everything. Working with LSE now.
- Many fixes. Fixed interrupt setting. Added data structures.
- Changed interrupt handling. Removed FARs. Added Kconfig options for selecting interrupts.
- Updated info and formatting.
- Formatting fixes.
- Formatting.
- Changed iten to regval.
- Removed Triggger
- Formatting fixes per Pull request.
- Changed private_types to have stm32_ prefix. Used depends on for DTS Kconfig Menu. Fixed formatting per PR.
- Fixed spacing of function prototypes.
- Fixed indent on line
- Added documentation for STM32H5 and Nucleo-H563ZI regarding DTS. Also added GPDMA support to STM32H5 documentation (previous PR). Made stm32_dts.c more modular. stm32_dts_activate is now much more readable. Added comments/descriptions to private functions. Lastly, added a nucleo-h563zi:dts configuration.
2025-07-23 15:08:02 +08:00
Martin Vajnar
150854c6f2 ESP_PCNT: add high and low limit Kconfig options
Signed-off-by: Martin Vajnar <martin.vajnar@gmail.com>
2025-07-22 13:09:02 -03:00
Filipe Cavalcanti
3468c8e0cf arch/risc-v: change offset for SPI Flash on Espressif devices
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-22 10:55:08 -03:00
Filipe Cavalcanti
a7cd6bb401 arch/xtensa: add E-Fuse support on ESP32S2
Adds support for e-fuse on ESP32S2 and fixes a gitignore issue.

Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
2025-07-22 10:55:08 -03:00
SPRESENSE
664277039e arch: cxd56xx: Fix bug that causes wake-up by unused gpio interrupt
Set level high for unused interrupt trigger to avoid waking up from cold sleeping.

Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
2025-07-22 16:21:26 +08:00
guanyi
ac5b38c9e5 arch/sim: avoid host-call being interrupted before getting errno
Sim use coroutine base on one thread in host to do switch context. but if we allow switch context with in one API (host-API and errno get), maybe the switch context from coroutine cause re-enter host-API call. Make the errno get behavior not work as expected.

Signed-off-by: guanyi3 <guanyi3@xiaomi.com>
2025-07-21 19:19:05 -03:00
xuxin19
956a50bb7d cmake(bugfix):add missing c++ toolchain search path
when libcxx or uClib++ is not selected, we use the default NUTTX cxx

Signed-off-by: xuxin19 <xuxin19@xiaomi.com>
2025-07-21 19:21:02 +08:00
chao an
9e53aab5b3 xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
common/xtensa_context.S: Assembler messages:
common/xtensa_context.S:134: Error: invalid register number (231) for 'rur' instruction
common/xtensa_context.S:283: Error: invalid register number (231) for 'wur' instruction
clang-10: error: Xtensa-as command failed with exit code 1 (use -v to see invocation)
make[1]: *** [Makefile:143: xtensa_context.o] Error 1
make[1]: *** Waiting for unfinished jobs....

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-07-21 12:56:31 +02:00
wangmingrong1
cbdc1a4108 toolchain/arm/clang: fix nuttx_find_toolchain_lib function error
Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-07-18 22:37:36 +08:00
wangmingrong1
d3dd43cb59 arch/arm32v8m/cmake: Fix clang's error in specifying cfg and target
1. -target should be in front, otherwise clang will not be able to find the corresponding libgcc.a
2. When using clang++ compiler to link, you also need to specify the corresponding arch, otherwise ld.lld will report an error due to arch mismatch.

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-07-18 22:37:36 +08:00
nuttxs
d1fababfc5 arch/xtensa: esp32(s3)_async_op() using nxsem_wait(), threads may
return early due to signal interruption (EINTR). This makes the
main thread think the async operation is done, but the background
worker thread is still running—risking access to freed memory,
race conditions, crashes or undefined behavior.

Using nxsem_wait_uninterruptible():the main thread waits until the
worker thread finishes, preventing these issues.

Signed-off-by: nuttxs <zhaoqing.zhang@sony.com>
2025-07-18 22:34:13 +08:00
wangmingrong1
1bdbf0effd toolchain/arm64/cmake: Corrected the writing of arm64 cmake search library
Align the writing style of arm cmake, and each compiler defines its own find library
function, otherwise use the default

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-07-17 19:17:55 +08:00
chao an
7352e8ebfa arm64/qemu: decouple qemu board from chip
decouple qemu board from chip to support custom boards

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-07-16 10:12:57 -03:00
Peter van der Perk
def76c90d5 imx95: eDMA5 Allow sharing with Linux
Allows to offset channels and thus sharing the controller with A-core
2025-07-16 01:19:05 +08:00
wangmingrong1
be3cd43a1e toolchain/armclang: Fix armclang config
In the toolchain, ARCH_TOOLCHAIN_XXX is used to select the compiler to be used. If clang is selected here, subsequent errors will occur

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-07-15 21:56:46 +08:00
chao an
382d38b4e0 arm64/zynq-mpsoc: fix race condition in txint handler
The tx int handler will call uart_xmitchars() to make a fake interrupt event,
but this is unsafe after enabling interrupts. This PR will add a critical section
to ensure that the txint process will not be interrupted by the IRQ

Signed-off-by: chao an <anchao.archer@bytedance.com>
2025-07-13 18:22:02 -03:00
paolo
b628aec268 arch/arm/rp23xx: spi unset peripheral before to modify Spi parameters
As done by Pico Sdk is better to unset SSPCR1.SSE bit before to modify
Spi parameters (Mode, Frequency as Bits)
2025-07-12 20:11:13 -03:00
wangmingrong1
51a82d5289 arm/clang: Fix crash caused by clang compiling with -mfpu=fpv5-d16 and -march=armv8.1-m.main+mve.fp+fp.dp
The above combination of compilation causes the compiler to crash:
 #1 0x0000000001fbe154 llvm::sys::CleanupOnSignal(unsigned long) (clang18/bin/clang-19+0x1fbe154)
 #2 0x0000000001f21203 llvm::CrashRecoveryContext::HandleExit(int) (clang18/bin/clang-19+0x1f21203)
 #3 0x0000000001fb7b7e llvm::sys::Process::Exit(int, bool) (clang18/bin/clang-19+0x1fb7b7e)
 #4 0x0000000000b25f0d (clang18/bin/clang-19+0xb25f0d)
................................................................................
................................................................................
This problem occurs in clang18 and above, and there are compilation instructions that are incompatible with GCC.
By following the recommended v8.1m corresponding fpu modification, no crash will occur
➜  NX git:(master) ✗ clang --target=arm-none-eabi -mfpu=help
clang: note: available multilibs are:
--target=thumbv8m.main-unknown-none-eabi -mfpu=none
--target=thumbv8m.main-unknown-none-eabi -mfpu=none -fno-exceptions -fno-rtti
--target=thumbv8m.main-unknown-none-eabihf -mfpu=fpv5-sp-d16
--target=thumbv8m.main-unknown-none-eabihf -mfpu=fpv5-sp-d16 -fno-exceptions -fno-rtti
--target=thumbv8.1m.main-unknown-none-eabi -mfpu=none
--target=thumbv8.1m.main-unknown-none-eabi -mfpu=none -fno-exceptions -fno-rtti
--target=thumbv8.1m.main-unknown-none-eabihf -march=thumbv8.1m.main+fp16 -mfpu=fp-armv8-fullfp16-sp-d16
--target=thumbv8.1m.main-unknown-none-eabihf -march=thumbv8.1m.main+fp16 -mfpu=fp-armv8-fullfp16-sp-d16 -fno-exceptions -fno-rtti
--target=thumbv8.1m.main-unknown-none-eabihf -march=thumbv8.1m.main+fp16 -mfpu=fp-armv8-fullfp16-d16
--target=thumbv8.1m.main-unknown-none-eabihf -march=thumbv8.1m.main+fp16 -mfpu=fp-armv8-fullfp16-d16 -fno-exceptions -fno-rtti
--target=thumbv8.1m.main-unknown-none-eabihf -march=thumbv8.1m.main+mve -mfpu=none
--target=thumbv8.1m.main-unknown-none-eabihf -march=thumbv8.1m.main+mve -mfpu=none -fno-exceptions -fno-rtti

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-07-11 20:36:35 +08:00
wangmingrong1
ae70e09810 toolchain/arm: Fix link parameter error
Fixed the problem that when using armclang, it cannot add a space after --scatter=

Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
2025-07-11 09:13:03 -03:00
kywwilson11
7abfbddb2f Add additional support for STM32H5 ADC
Put define guard around call to adc_oversample. Fixed formatting.
2025-07-11 09:59:31 +08:00
Kerogit
d3da5e633c arch/avr/avrdx/avrdx_serial: make uart_ops_s structure const
The structure never changes and should be therefore marked as const.

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2025-07-10 12:21:40 -03:00
Kerogit
d9269112ee arch/avr/avrdx: do not copy const variables into RAM
AVR uses Hardward architecture with separate address space for program
memory (flash) and data memory (RAM). Normal program flow can only
access data memory which means that all variables - including const
variables - have to be copied into RAM to be accessible. (This happens
automatically during startup.)

It is possible to work around this limitation in software but that
can have severe impact on performance and/or API complexity. It is hardly
feasible to change NuttX interfaces in a way that would allow to make use
of this workaround.

On newer AVR families, there is an alternative option enabled by this patch.
These chips map part of their program memory (a 32kB window) into data
memory address space. This patch leverages this feature and adds support
for placing const variables into the mapped window. No copy to RAM is done
for them.

Const variables are therefore loaded directly from flash (not consuming
RAM) while still being available to be used by any NuttX interface.

Linker script of breadxavr board is changed to make use of these changes.

Tested by verifying string addresses - parameters in printf call
in a custom application (and also by running the application and verifying
its output.)

Documentation tested by build.

Signed-off-by: Kerogit <kr.git@kerogit.eu>
2025-07-10 12:21:40 -03:00
sanezek
7a32fed563 arch/arm/stm32h7: support for /dev/random device
Enabling support for random device on stm32h7 arch. Driver copy pasted from arch/arm/stm32.

Signed-off-by: sanezek <sanezek@protonmail.com>
2025-07-10 09:52:58 -03:00
kywwilson11
0c1f9d482d Added DMA support for H5. Also added ADC DMA support.
Added logic to set hasdma to false. This is needed to enable or not enable interrupts on a per ADC basis. Made other minor formatting changes.

Fixed build issues with non ADC/DMA configurations.
2025-07-10 09:51:23 -03:00
paolovolpi
e1e9ea2e81 RP2350B has 48 gpio, highers 16 accessed by "HI" registers 2025-07-10 13:45:33 +08:00
Eren Terzioglu
af8e43e7f2 arch/xtensa: Bugfix I2C Slave build error for esp32[-|-s2|-s3]
Fix build error for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:18:06 +08:00
Eren Terzioglu
f07141244c arch/risc-v: Bugfix I2C Slave build error for esp32[-c3|-c6|-h2]
Fix build error for risc-v based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
2025-07-09 12:18:06 +08:00