If both SPI Flash support (`CONFIG_ESP32S3_SPIFLASH`) and PSRAM
(`CONFIG_ESP32S3_SPIRAM`) are enabled, the PSRAM can only be
assigned to the user's heap (`CONFIG_ESP32S3_SPIRAM_USER_HEAP`).
Additionaly, `CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK` must be
set because the system will end up allocating tasks' stacks from
the external PSRAM. This has an impact when dealing with SPI flash
operations because the cache must be disabled and the running task
should not rely on any data from the PSRAM. To accomplish that, It
offloads the SPI flash operation to a work queue (which, by
definition, allocates its heap from the kernel heap).
The same (assigning the PSRAM to the user's heap) is valid when the
Wi-Fi is enabled because the lower-half driver requires data being
allocated from the internal memory (which can only be achieved by
allocating from the kernel heap when both the kernel and user heaps
exists).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Use this command to extract archives.
Not all architectures are modified, only those commands I know
or could be logically deducted from the rest were added.
Signed-off-by: Stepan Pressl <pressl.stepan@gmail.com>
The interrupt handler accesses the device as well as the driver's private
data. Thus, must take the big kernel lock in SMP mode to protect them.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
In SMP mode one CPU can be executing the MMC interrupt while another CPU
disables (e.g. via watchdog timeout). As it is disabled the other CPU
assumes it's safe to start configuring the device after this.
This causes a leak in the driver's private data as well as a mutual
exclusion leak on the device itself.
Fix this by aborting any triggered interrupt by checking whether it's
even enabled.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Update board reset with BOOTROM functions calls
- normal reboot
- reboot to bootloader
normal reboot and reboot bootloader now possible from nsh
Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
Currently the irq handler checks many reserved bits, which is
a waste of resources:
1. pending_rx_ep bit 0 is reserved (always 0)
2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4
defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the
rest are reserved
Fix this by checking only the relevant bits.
Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
As emmcsd driver does not support separate WRCOMPLETE interrupt the
SDIOWAIT_WRCOMPLETE event shall not be waited.
The SDIOWAIT_TRANSFERDONE event indicates that both "transfer done"
and "write complete" events are completed.
mpfs_sendcmd() shall not wait for data lines ready before
sending commands to the card. This prevents mmcsd driver
to poll card busy status prior to next activity after
a write operation.
Add capture source files to the makefile pipeline.
STM32H7_CAP to STM32H7_TIMX_CAP for clarity.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
Add documentation for changes made in #16809.
Add an example defconfig for a nsh build with the capture example.
Replace the STM32H7_CAP option with just CAPTURE as the guard for the
lower half driver.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
Enabling a higher channel of the internal ADC had the effect of
initializing the lower ones as well. Now that happens only if
actively requested.
Also, the functions for handling the internal ADC did not follow
the typical naming used by comparable modules for the same arch
and were renamed for coherence. Informational logging calls were
also made slightly more useful and discernible in case of having
multiple ADCs.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
Add support for the RP2040's GPIO output override capabilities.
Implementation inspired by the uniqueid functions for the same arch.
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
When delivering a signal to a kernel task, or in CONFIG_BUILD_FLAT with MMU
enabled, the REG_SCTLR_EL1 needs to be stored for exception return.
Otherwise 0 is restored to the register at exception return, MMU is switched off
and the system crashes.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
The strings "RPC2040" and "RP2040_IO_BANK0_GPIO0", presumably typos,
were used in place of respectively "RP2040" and "RP2040_IO_BANK0_GPIO".
Signed-off-by: Niccolò Maggioni <nicco.maggioni+nuttx@gmail.com>
This patch fixes an incorrect call to stm32_cap_initialize() in
stm32_bringup.c: the call was made without the channel parameter.
Instead of adding the channel in the call, the channel is selected by
stm32_cap_gpio() (first available channel).
This patch also fixes incorrect driver registration in
drivers/timers/capture.c: the driver was registered with the wrong
name (/dev/cap -> /dev/capture). Also added more error checking in
cap_register_multiple().
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
This PR add support to USBHOST on iMXRT1052 ARCX-Socket-Grid board
and add a USBDISK board config example.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
This commit introduces a timer capture driver for the STM32H7 series
ported from the STM32 F series.
The main changes include:
- A new generic timer capture driver for STM32H7.
- A lower-half driver to integrate with the NuttX capture subsystem.
- Kconfig options to enable and configure capture for various timers.
- Pin definitions for TIM1-4 capture inputs on the nucleo-h743zi.
- An update to `cap_register_multiple` to handle multiple device registration.
- An update to `stm32_bringup` to register the capture drivers.
The current implementation is based on a driver originally for PWM input,
and as such, it calculates duty cycle and frequency. It is also limited
to a single capture channel per timer.
The original implementation's `stm32_cap_init` in
`arch/arm/src/stm32h7/stm32_capture.c` has been modified to accept a
channel number instead of using a hardcoded 0 through
`STM32_CAP_CHANNEL_COUNTER`.
This serves as a foundation for future development of more comprehensive
input capture capabilities on STM32H7 platforms.
Tested by polling and reading `/dev/cap0-4` with
`ioctl(fds[i], CAPIOC_FREQUENCE, freq)` while sending a square wave signal to
appropriate pins and checking frequency.
Also tested by bypassing upper half driver and setting up capture on
TIM4 channels 1-4 as explained in #16762.
Signed-off-by: Côme VINCENT <44554692+comejv@users.noreply.github.com>
This fixes the same issue for other targets, which was already fixed for
xtensa in commit 50d94863.
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[xx]) will enable them if they were
enabled in the context.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Clear dma interrupt flags as before.
Change HTEF to HTF, fixes typo.
Remove ALL_FLAGS define. Clear CXFCR with all 1s like other instances do.
Handle half-transfer interrupt only if in circular mode.
Add ADC_HAVE_DMA guard around adc_rstart_dma. It is needed because priv->circular is guarded by ADC_HAVE_DMA.
After the signals have been delivered, the local irqs need to be
disabled until the context switch. But just calling
leave_critical_section(regs[REG_PS]) will enable them if they were
enabled in the context.
Any interrupt on this cpu before xtensa_context_restore() would set
the rtcb->xcp.regs to NULL, causing a crash in context restore.
Fix this by calling leave_critical_section(up_irq_save()) instead.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Many iMXRT MCUs have internally two USB OTG controllers, however
NuttX currently only supports one USB controllers. This patch will
prepare the "house" to support both ports at same time.
Signed-off-by: Alan C. Assis <acassis@gmail.com>
PIC32CZ CA70 family is pin to pin and binary compatible with
SAMV70/SAME70 families, therefore the support is placed in samv7
directory. The only difference is larger RAM memory compared to SAM
families.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
- Committing initial code for DTS. Missing ISR. Works for PCLK1. Cannot get to work for LSE.
- Pushing everything. Working with LSE now.
- Many fixes. Fixed interrupt setting. Added data structures.
- Changed interrupt handling. Removed FARs. Added Kconfig options for selecting interrupts.
- Updated info and formatting.
- Formatting fixes.
- Formatting.
- Changed iten to regval.
- Removed Triggger
- Formatting fixes per Pull request.
- Changed private_types to have stm32_ prefix. Used depends on for DTS Kconfig Menu. Fixed formatting per PR.
- Fixed spacing of function prototypes.
- Fixed indent on line
- Added documentation for STM32H5 and Nucleo-H563ZI regarding DTS. Also added GPDMA support to STM32H5 documentation (previous PR). Made stm32_dts.c more modular. stm32_dts_activate is now much more readable. Added comments/descriptions to private functions. Lastly, added a nucleo-h563zi:dts configuration.
Set level high for unused interrupt trigger to avoid waking up from cold sleeping.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Sim use coroutine base on one thread in host to do switch context. but if we allow switch context with in one API (host-API and errno get), maybe the switch context from coroutine cause re-enter host-API call. Make the errno get behavior not work as expected.
Signed-off-by: guanyi3 <guanyi3@xiaomi.com>
